Conventionally, semiconductor memories such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”) are in widespread use. DRAM is very common due to its high density with a cell size typically between 6F2 and 8F2, where F is a minimum feature size. However, DRAM is relatively slow, having an access time commonly near 20 nanoseconds (“ns”). Though SRAM access time is typically an order of magnitude faster than DRAM, an SRAM cell is commonly made of four transistors and two resistors or of six transistors, leading to a cell size of approximately 60F2 to 100F2.
SRAM memory designs based on a negative differential resistance cell, such as a thyristor-based memory cell, have been introduced to minimize the size of a conventional SRAM memory. A thyristor-based memory may be effective in stand-alone and embedded memory applications. Examples of thyristor-based memory cells are described in additional detail in U.S. Pat. Nos. 6,767,770 B1, 6,686,612 B1, 6,690,039 B1, 6,815,734 B1, and 6,818,482 B1.
Unfortunately, parasitic transistors, whether existing internally to a thyristor-based memory cell (“intra-cell parasitic transistors”) or created by thyristor-based memory cells connected together in an array (“inter-cell parasitic transistors”) may negatively impact performance. For example, an inter-cell parasitic transistor may facilitate charge to be transferred from one thyristor-based memory cell to another commonly coupled thereto. Charge from one thyristor-based memory cell injected into an adjacent thyristor-based memory cell may make the adjacent memory cell less stable or may make both memory cells less stable. Moreover, an intra-cell parasitic transistor may undesirably impact stability or operability of a thyristor-based memory cell by facilitating unwanted charge transport within such cell.
Accordingly, it would be desirable and useful to provide means to reduce one or more effects of parasitic transistors associated with one or more thyristor-based memory cells of a thyristor-based memory array.